Design And Analysis Of Processing Elements For Portable Systems

The main objective of this paper was to analyze the best possible implementation style for the data path designs so as to optimize their performance according to the application domain as well as field of use. In this project, we present the design and analysis of two new processing elements for reconfigurable computing. We also present a circuit-level implementation of the data paths in static and dynamic design styles to perform arithmetic and logical operations, and also explore the performance-power tradeoffs involved. We also Present the two data paths, the data path I proposed the architectures for different levels of granularity, the data path II proposed the architectures for improving different levels of granularity, and also proposed Floating Point Precision Element(FPPE) based on the generalized architectures. The proposed data paths and FPPE are implemented by using static, domino and datadriven dynamic logic (D3L) models for improving of delay, area, power and Power Delay Products (PDP) with different parameter variations in different technologies like 180nm, 120nm and 65nm.in this paper we presents the comparison between two data paths, Data Path I was poor performance when compared to the Data Path II in case of Power delay Product(PDP) and also Data path I was poor performance it consumes higher power compared to the Data Path II, from the above comparison the data path II was the best processing element for systems. Finally the propose FPPE was executed for floating point numbers